Power-gating schemes for super-threshold FinFET CML circuits

In high-speed applications, FinFET Current Mode Logic (FinFET CML) circuits are potential alternative one. However, the FinFET CML circuits have large power consumptions in standby operation because of their constant biasing currents, which badly limits their application in portable devices. This paper presents power-gating schemes for the super-threshold FinFET CML circuits to reduce the standby power dissipations. The structure and operation of the proposed power-gating scheme are addressed in detail. The results show that the power dissipations of FinFET CML circuits can be greatly reduced at super-threshold regions by shutting down their idle logic blocks without performance degrading.