Estimation of formal verification cost using regression machine learning

Formal Verification is a computationally expensive step in the verification of today's complex hardware designs. Effective results can be obtained from formal runs by planning ahead the effort and cost that are required for them. Additionally estimating in-advance the expected formal's complexity promotes a lot of potential tricks and clever setup techniques to overcome the initial push-button capacity limitation of the formal verifies and improve their capabilities to handle designs with higher complexity. This paper illustrates the application of regression machine learning (ML) techniques to build an estimation model for the cost of formal verification. Up to 10,000 formal verification runs on RTL designs with good varieties of design/properties attributes are used to learn the relationship between HW designs and the final formal cost in terms of formal run time. We demonstrate the use of Ridge-Regression to decide on the bias-variance trade-off during the regression-model design step as well as the application of Lasso-Regression for the feature selection phase. Finally a comparison between the proposed multiple linear regression approach and another non-parametric K-nearest neighbors kernel based regression technique is done to conclude on the presented work. Our results indicate how the proposed model managed to estimate with reasonable error ratio the expected formal verification effort for new-to-verify HW designs.