A novel Adiabatic SRAM design using Two Level Adiabatic Logic

Memory is a component of almost every chip and plays a very important role in today's world. In applications like cardiac pace-makers, Satellite thrusters etc., where accessibility of the chip in the device is extremely restricted, once installed it becomes imperative that the chip consumes very less power. Designing via Adiabatic logic shows great improvements in power dissipation reduction over the conventional designs. In this paper we propose two designs for SRAM using Two Level Adiabatic Logic (2LAL) and compare their power dissipation with a conventional SRAM cell. The notable feature of the designs is that it is essentially a zero-CMOS transistor design, since only transmission gates have been used to design the RAM and the design involves zero CMOS inverters for cross-coupling as seen in almost all designs until now. The simulation was carried out in Cadence Virtuoso and the simulator used was Spectre. The power dissipation was reduced by a factor of 10 as compared to the conventional SRAM.