All-digital phase-locked loop used in a clock recovery algorithm

In a digital communications system, one of the essential functions is clock recovery. In this paper a first order all-digital PLL, which is used to recover the embedded clock from an S/PDIF (Sony Philips Digital Interface) transmitter, is described. Simulations have shown that the performance of the ADPLL can meet the requirements of the IEC-958 standard. This is achieved while using a low sampling rate which allows for low power requirements. All digital circuits are also advantageous in VLSI design.