Design and analysis of double edge triggered clocked latch for low power VLSI applications

In this paper, implementing for double edge triggered flip flop is introduced. The double edge triggered flip flop is used to reduce number of clocked transistors in the design. The effective method of the double edge triggered paradigm and n-MOS transistor logic of the new proposed implicit pulsed double edge triggered flip-flop (PIPDETFF) is proposed. The power aware technique of the sleep and sleep-bar is used to the clocked latch of the paradigm to present the circuit in idle mode and reduced the power consumption. The power consumption of clocked latch is lower than that of the clocking distribution network. The design can be implemented in DSCH and MICROWIND 3.1 CMOS layout tool. Analysis of the performance parameters shows that performance of PIPDETFF is superior compared to the conventional flip flop. A 10.50% to 54.53% reduction of power can be achieved in proposed implicit pulsed double edge triggered flip-flop (PIPDETFF).