Power reduction in sequential circuits using logic styles

Now-a-days, power reduction in an IC is a serious concern. There is high need for circuits which consume less power, mainly for portable devices which run on batteries, like Laptops and hand-held computers. The memory elements consume 70 percent of the total power in an IC. As flip-flops are the memory elements used in any portable devices, it is necessary to reduce the power consumption in flip-flops. It will help us to reduce the power consumption in an IC to a major extent. In this paper, D flip flop is designed using various logic styles to reduce the power and its power consumption is compared. Microwind 3.1 version is used for the design and analysis.