An FPGA Based Multi-functional Signal Generator Using SOPC Design Methodology

This paper presents an FPGA based miniature, multi-functional signal generator with digital controller inside to adapt applications such as wireless sensor network (WSN) and software define radio (SDR) system. To reduce design complexity and decrease development time, this work adopts a novel SOPC design methodology, which means using embedded soft-core microprocessor Nios II and EDA tool Quartus II to accomplish design process. Nios II is a configurable and optimizable soft-core CPU which is embedded in FPGA. Using characteristics of Nios II, we put together every logical units that system needs and implant them into a single FPGA chip. Then uses the Avalon bus to connect with Nios II's Avalon bus main port (instruction and data control port) with function choose keys, LED display units and other peripheral equipment. Realize a signal generator system that is flexible to reduce, extend, with low power consumption, and has System on Programmable Chip (SOPC) function which means the system's software and hardware is online programmable and reconfigurable. The system design process uses SOPC design methodology.