FinFET — One scale up CMOS: Resolving scaling issues

Device scaling is the prime factor to achieve less area and high performance. Short channel devices produce more leakage currents. Continuous device scaling increases side effects and they become very severe beyond 45nm technology. To meet the latest technological changes, an alternative to device scaling needs to be found which could be able to hold advantages of device scaling and reduce the side effects produced beyond 45nm technology which leads to change the MOSFET device structure to FinFET, TFET. In this paper the conventional modeling procedures of MOSFET and FINFET are explained depending upon their structural and characteristic differences. The behavior of FINFET can be studied using HSPICE and TCAD Software.