A dead-time minimized inverter by using complementary topology and its experimental evaluation of harmonics reduction

This paper proposes a “complementary inverter”, which consists of p-channel and n-channel MOSFETs in a leg. This configuration can minimize dead time; therefore, harmonics generated by the dead time can be eliminated, without any compensation controls. Possible leg configurations and appropriate gate driver are discussed. Model for estimating dead time is shown and was confirmed by experiments with a half-bridge inverter. The minimum dead time of 130 ns was achieved in a fabricated prototype. The advantage of the minimum dead-time operation by the complementary topology was verified by applying to a 400 W grid-tied inverter with 100 kHz switching frequency and a reduced impedance of the grid connecting inductor to 1.5% of the nominal, and 2.3% current THD (total harmonic distortion) was achieved.