A methodology for behavioral synthesis of analog systems

In this paper, we present a behavioral synthesis methodology for analog systems (CMOS analog integrated circuits) described in VHDL-AMS. First, a compiler transforms the behavioral descriptions into a signal-flow graph that describes the system functionality. Then, an exploration engine, consisting of a branch and bound based architecture generator and a genetic algorithm based constraint transformation and component selection method, explores distinct implementation alternatives for a signal-flow graph. The exploration engine tightly interacts with an analog performance estimator. The result of the synthesis process is a sized net-list of components that implements the specified behavior, and meets the performance constraints.