Simulation of wafer-scale GTO thyristors in circuits

A simulation technique that allows the study of large area power devices composed of many outwardly identical elements operating in a realistic power circuit has been developed. Results are presented showing the transient redistribution of current between a pair of GTO thyristor elements during turn-off under the influence of the power circuit. The method is validated by comparing simulated results with experimental measurements. Variations in carrier lifetime. diffusion uniformity, and gate contact position are studied, and they are shown to significantly alter the turn-off performance. Conclusions are drawn concerning the reliability of large area latching power devices with process inhomogeneity.<>