Buffered Spin-Torque Sensors for Minimizing Delay and Energy Consumption in Global Interconnects

We propose a low-voltage, low-current interconnect architecture using buffered/pipelined spin-torque (ST) sensors to optimize the overall delay and energy consumption. Conventional techniques for reducing energy consumption on long interconnects involve low voltage swings on interconnects or current-mode interconnects. However, such techniques require power-consuming voltage converters or trans-impedance amplifiers at the receivers. ST-sensor-based receivers have recently been introduced that can operate without analog components at the receiver. As a result, the energy consumption is lower compared to existing techniques. However, the delay can be relatively high in these networks for long Cu-lines since these methods do not accommodate conventional buffering schemes for delay minimization. Here, we propose the use of ST buffers in the line in addition to ST-sensing at the receiver. The buffers and sensors used in our design consist of a magnetic strip of two magnetic domains separated by a domain wall. The domain wall can be moved by a current flowing through an adjacent spin-Hall metal which leads to a change in the resistance of the receiver. This resistance change is easily sensed using simple CMOS components. With the introduction of buffering for ST-sensor interconnects, the proposed method can be highly efficient in optimizing the energy-delay performance for long, global on-chip or off-chip lines. Our simulation results indicate that for a 10 mm line in 45 nm CMOS technology, the energy consumption with ST-sensing is about 2 percent that of full-swing, and about 4 percent that of low-swing, CMOS interconnects. Moreover, the delay is much lower than low-swing, and comparable to full-swing, CMOS designs.