Reconfigurable FET SPICE model for design evaluation

A lot of works have been done to propose and study alternative devices for future electronics. Between the possible candidates (Tunneling FETs, stacked nanowires...), Reconfigurable FET (RFET) appears as an interesting option to achieve reprogrammable logic in future circuits. The first step to evaluate the potentialities of new devices at circuit level is compact modeling. For the first time we propose a simple compact model of Fully-Depleted SOI RFET validated by TCAD simulations. Our model is implemented in Verilog-A to evaluate circuit-level performance with conventional CAD tools.