Implementation of programmable digital sigmoid function circuit for neuro-computing

A programmable digital sigmoid function generator circuit has been designed and implemented. The circuit is based on second order approximation of the nonlinear sigmoid function and utilizing its characteristics. It offers an easy way of changing the steepness of the function in the transition state. In addition, the squaring function operation was implemented using combinational logic. This offers a compact realization of the system as a parallel bit architecture. The maximum output error is .047 and the average error is within 0.01. Simulations show that the circuit operates satisfactorily up to 50 MHz. The digital VLSI circuit has been fabricated using MOSIS/AMI N-well 1.2 /spl mu/m CMOS double metal process. It occupies an area of 900/spl times/450 /spl mu/m/sup 2/.