A RISC-V instruction set processor-micro-architecture design and analysis

Micro-architecture design and analysis of a RISC-V instruction set processor has been articulated in this paper. Instruction Set Architectures (ISAs) for processors from Intel, AMD, Intel, MIPS etc. is protected through IP Rights and Infringements. Few ISAs do exist as open-source viz. Open RISC, SPARC, RISC-V etc. RISC-V ISA has been evolved from the efforts at University of California, Berkeley and has been open sourced as BSD license. This paper details the microarchitecture design and analysis of a 5-stage pipelined RISC-V ISA compatible processor and effects of instruction set on the pipeline / micro-architecture design. The design have been analyzed in terms of instructions encoding, functionality of instructions, instruction types, decoder logic complexity, data hazard detection, register file organization and access, functioning of pipeline, effect of branch instructions, control flow, data memory access, operating modes and execution unit hardware resources. The processor has been micro-architected, simulated using Blue-spec System Verilog, synthesized and analyzed on FPGA platform and 65nm and 130nm technology nodes for ASIC. The synthesis results are compared and analyzed with similar efforts on RISC-V ISA based processor core.