Spatio-Temporal Bias-Tunable Readout Circuit for On-Chip Intelligent Image Processing

A new 96 × 96 array of 30 μm × 30 μm readout integrated circuit (ROIC) with an individual pixel tunable bias control is demonstrated. Detailed IC design, test structures, readout circuit building blocks, and applied techniques are discussed. The new ROIC is capable of providing a large voltage swing for the bias in both positive and negative polarities to each individual pixel, independently. These enhanced functionalities are achieved by modifying a capacitive transimpedance amplifier (CTIA) CMOS ROIC architecture. An FPGA-based test bench has also been developed to test and characterize the new ROIC system, for which software and hardware are described in detail. The test chip has been fabricated with 2P4M 0.35 μm high-voltage CMOS technology, where the bias voltage range is ±5 V and the output swing range is ±3.9 V. The demonstrated ROIC is an ideal infrastructure for implementation of region of interest enhancement and a solid base for infrared multispectral acquisition targeting an infrared retina.