Multi-VT design of vertical channel nanowire FET for sub-10nm technology node

In this work, a feasible multi-V_T modulation strategy in vertical nanowire FETs (VNWFETs) combining asymmetric halo doping with nanowire diameter is proposed and verified by TCAD simulation. The results show that halo configuration close to source side exhibits larger V_T-tuning range and better SCE controlling. Moreover, adjustment of halo doping concentration and nanowire diameters can be adopted to provide at least three V_T choices for 7nm technology node. It is demonstrated that VNWFETs is quite promising for SOC application.