Design and implementation of a power and area optimized reconfigurable superset parallel prefix adder

This paper a new structure of superset adder is introduced. The proposed design comes with three major contributions. First, the design preserves the best points of performance while it reduces the others with the gain of total area reduction. Second, the MUX-block is removed and ROM control logic is introduced for topology selection schemas. Third, the building blocks of the main core including DOT and Semi-DOT are designed with Source Coupled Logic (SCL). In our design, the higher operating frequency than the cross-over frequency of CMOS speeds up the design without increasing the power consumption. Therefore, the proposed design operates in low-power mode at all of its designated frequency range. Simulations are performed with spice @180nm. The non-optimized CML mode design consumes 64uw against 1400uw of CMOS at 1GHz. The final optimized design performs156fJ PDP in 1.3v-1.8v swing @1.8v supply versus 169 and 186fJ in previously reported results. The proposed design outperforms CMOS in the frequency range from 25MHz to 1GHz with constant power.