Low power design of binary signed digit residue number system adder

Due to the increasing spread of digital computing, investigation of various number representation systems in the digital field seems necessary. In general, the number representation systems regarding their applications can be classified in two areas: general-purpose and specific-purpose. Binary Signed-Digit Residue Number System (BSD-RNS) is one of the specific-purpose and optimized number system. In fact with blending RNS that decreases the length of operands and BSD that has redundancy property, we can achieve BSD-RNS that can perform calculation in parallel. On the other hand, due to limited access to the energy resources, reducing power consumption can also increase system popularity. The addition unit as a basic computational unit can play an important role in overall system performance. Therefore, in this paper, it is intended first to introduce three basic adder structures for BSD-RNS. Then we propose low power adders for the moduli set {2^{n 1},2ⁿ,2ⁿ+¹} based on 2's complement, 1-out-of-3, and Pos-Neg BSD-RNS number system. Compared to conventional structure of BSD-RNS adders, proposed adders have 10%, 70%, and 21% less power than the existing efficient BSD-RNS adders for 2's complement, 1-out-of-3, and Pos-Neg encoding, respectively.