A novel low phase noise and low power DCO in 90 nm CMOS technology for ADPLL application

A novel structure with low phase noise and low power dissipation fully differential cross-coupled CMOS LC-DCO is presented. Two effective techniques including adding two digitizer and utilizing two top switching transistors, are used in order to optimize the phase noise. The performance of the proposed DCO well meets all the requirements for low phase noise and low power All-Digital Phase Locked-Loop (ADPLL). Simulation results are obtained by the Cadence IC Design software in 90nm CMOS technology with Spectre simulator. Carrier frequency of Proposed DCO is tuned in the range of 10 to 10.7 GHZ. The measured phase noise at 1 MHz offset from the 10 GHz carrier frequency is around -116 dBc/Hz, while the DCO consumes 4.9 mw at the 1.2 volt supply voltage and finally, FOM is -189 dBc/Hz.