Dynamic body bias for 22 nm FD-SOI CMOS Technology

This paper presents a digitally controlled dynamic body bias voltage generator, designed to explore the performance characteristics of Global Foundries 22 nm FD-SOI CMOS state-of-the-art technology. The key feature is represented by the dynamic behavior of the energy-speed trade-off between static power and local variations, which is determined by applying a variable positive or negative voltage to the transistor's back-gate. In this design, the negative voltage is in-ternally generated by a charge-pump and the number of external components is then limited to one external buffer capacitor. The back bias voltage can be changed from 2 to -2 V in 1 mus for a maximum well capacitance of 6nF, which corresponds to an active area of 1.8 mm(exp 2). The dynamic bias voltage, which is applied to the nMOS and pMOS back-gate, is independently controlled with a digital word, achieving a step-size of 100 mV.