Design and comparative analysis of binary and quaternary logic circuits

The project presents the design of high performance quaternary Combinational circuits for lower power dissipation. Most of the digital electronic systems are based on the binary logic design which is limited by the requirement of interconnections which increases the chip area. The solution to this problem can be achieved using multi valued logic (MVL)/Quaternary logic. Most of the authors used methods which required Quaternary to Binary and Binary to Quaternary conversion for any arithmetic and logic operation and achieved satisfactory performances. Our aim is to develop MVL/Quaternary logic for combinational circuits under case study without converting these levels into binary logic and vice-versa. It will reduce one additional step, and improve the performance offering less chip size, saving more power. The design is targeted for 0.18um CMOS technology and the design tool for simulation will be Advanced Design System tool (ADS).