Research on thermal-electric coupling effect of the copper pillar bump in the flip chip packaging

In this study, a 3D copper pillar bumps model was established to investigate the reliability of the interconnection under thermal-electric coupling. In order to ensure the accuracy of the model, infrared thermography was used to verify the simulation of temperature distribution. The test not only proved the feasibility of this model, but it also indicated impact of Joule heat effect on temperature distribution. In the simulations, the results of the temperature, current density and stress distributions were analyzed. Based on the simulations, the thermal-electric coupling reliability of partial locations where failure might occur was discussed. It was found that, the trends of stress and temperature have a similar parabolic relationship with the current density. And current density variation could not change the distribution of the areas which high stress concentrated on. When the current density applied on solder is larger than 5.5×10⁴ A/cm², the maximum thermal gradient in solder could exceed 1×10⁵ K/m, thermal migration of metal atomics would occur in the bottom of solder. In addition, due to the effects of electro-migration and stress concentration, the upper surface of solder and the ultralow-k layers are considered to be the weak points for the copper pillar bump-type packages.