Failure mechanism study of power packages during MSL and temperature cycling test with finite element analysis

For power microelectronic packages, the requirement for moisture absorption level (MSL) is quite high, usually level 1 of JEDEC standard is requested. And the temperature has larger gap during temperature cycling in qualification. With such stringent requirements, these two test conditions are most frequently barrier due to the failure of interface. To better understand the failure mechanism difference in these two tests, an experiment was carried out. Here several packages are selected, they share the same leadframe design and package size, with gradually increasing chip size. Two similar epoxy mold compounds (EMC) with different resin content are also included during the study. All of the packages go to planned power package reliability test, the failure is recorded at both MSL test and temperature cycling. Results show that with the same design of leadframe and package size, the failure is significantly dependent on EMC selection and chip size. In order to address the EMC difference and chip size impact, finite element analysis is done with all these packages during MSL and temperature cycling test. Firstly, all the temperature dependent properties such as young's modulus and CTE (coefficient of thermal expansion) are measured in house, some of the moisture parameters are also measured. Then the stress is compared at the relative delaminated interface at specific temperature. With such study, the sensitive parameters of EMC property and chip size in different test conditions are explored.