A high-throughput, low power architecture and its VLSI implementation for DFT/IDFT computation

A recursive algorithm for computation of both forward and backward DFT has been proposed where the common entries in the decomposed matrices are factored out in order to reduce the number of multipliers needed during implementation. The derived algorithm is essentially the band-matrix-vector multiplication with matrix bandwidth of 3. By exploiting the heterogeneous dependency graphs for the matrix-vector multiplication and using an efficient mapping technique, only log/sub 2/N adders and log/sub 2/N-1 multipliers are needed to compute the DFT of size N, a great saving from a previously proposed systolic architecture which calls for 3log/sub 2/N adders and 3log/sub 2/N multipliers. Furthermore, due to the simplicity and regularity of the architectures, it is possible to design a low power processor by turning off the hardware components of no operation at proper time steps. VLSI implementation of the DFT/IDFT processor with distributed finite state machine (FSM) for timing control is also presented.