Experimental approach for feasibility of superlattice FETs

Steep subthreshold-slope (SS) devices are attracting much interest because of their capability of reducing the power dissipation in digital ICs. However, the mechanism for obtaining a steep SS often interferes with the low on-resistance that is required for a high on-current. The introduction of a doped superlattice into the source was recently proposed as a solution to this problem. However, to our knowledge, no one has yet reported an experimental trial for the same. In this study, by using vertical double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication processes, we fabricated FETs with an n-doped InGaAs/InP superlattice source, to confirm the feasibility of the superlattice FET. A superlattice FET with a 16-nm-wide mesa was fabricated. The observed I-V characteristics showed an on/off ratio of over 10⁶, which is necessary for observing the features of the superlattice FET. However, a plateau in the I-V characteristics (which is a feature of the superlattice FET) was not observed.