A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs

This work demonstrates for the first time a three-dimensional (3D) stacked hybrid P/N layer for p-channel junctionless thin-film transistor (JL-TFT) with nanowire (NW) structures. Relative to conventional stacked devices, the 3D stacked hybrid P/N JL-TFT exhibits a high I_on/I_off current ratio (>10⁹), a steep subthreshold swing (SS) of 70 mV/dec, a low drain-induced barrier lowering (DIBL) value of 3.5 mV/V; these properties are achieved by reducing the effective channel thickness that is determined by the channel/substrate junction. The developed stacked hybrid P/N exhibits reduced low-frequency noise, less sensitive temperature coefficients and performance variation in both threshold voltage (V_th) and SS, and so is suit for high-density 3D stacked integrated circuit (IC) applications.