Analytical decomposition of power delivery network response for ramp loads

Minimizing power supply voltage noise is critical for high performance microprocessors. This paper uses time domain analysis to explore dependencies between design parameters, voltage response and impedance profile for ramp type loads that are common to compute logic blocks. It is shown that the conventional impedance profile based design is not sufficient. In addition the analysis clarifies non-intuitive behaviors of the voltage response, and leads to guidelines for design space exploration.