A compaction based MT filling technique for low-power test set generation

VLSI testing plays a major role in verifying the functionality of the design before manufacturing the chip. There is a need to verify the chip at the design level itself so that if the functionality does not match the design specifications, the design can be corrected easily. If the defect is found after manufacturing the chip, it costs ten times more to test the chip at a higher level. This is given by rule of ten. The power dissipation during testing of chip is very high and it has become a challenge for the design and test engineers. The proposed approach addresses this issue by means of generation of test sequences, compacting them, extracting functional test cubes, x-filling the test cubes such that the switching activity minimization is ensured by keeping the fault coverage same. All the algorithms in the proposed approach are implemented using c programming and the same is applied to ISCAS'85 and ISCAS'89 benchmark circuits Switching activity, fault coverage before and after employing proposed approach is determined for the ISCAS benchmark circuits.