High performance ternary adder using CNTFET

This paper presents two new designs to implement a ternary half adder using Carbon Nanotubes Field Effect Transistors (CNFETs). Ternary logic is a promising alternative to conventional binary logic, since it is possible to accomplish simplicity and energy efficiency in modern digital design due to reduced circuit overhead such as interconnect and chip area. In this paper the authors are presenting two different novel ternary half adder circuits using ternary decoders and binary logic gates. The circuits are simulated using HSPICE to obtain power, delay and power delay product. The circuit performances are compared with the recently reported designs. The proposed ternary adders show delay and power advantage up to 40 and 39% with less transistor count. So, use of these half adders in complex arithmetic circuits will be advantageous.