An efficient architecture for improved reliability of cache memory using same tag bits

Cache memories are very important for improving the system performance such as in case of microprocessors. Since cache memory contributes a significant part to the complete system power dissipation and hence research undertaken in this paper identifies the tag bit errors when the data is fetched through associative cache memory mapping technique. The errors are rectified and overcome by a new technique, called as direct cache memory mapping. It has capability to reduce architectural complexity. The newly proposed technique has shown results with reduced power consumption compared to the existing techniques. The power consumption for the existing technique is at about 0.07 watt where as for the proposed technique is about 0.042 watt. The power consumption is, therefore, reduced by a margin of 40% compared to the existing technique.