VLSI design of high speed Vedic Multiplier for FPGA implementation

In the modern world of digitization, processing of data in real time requires an increase in the operating speed of a system. The processing more often than not utilizes multiplication which is time consuming and introduces considerable amount of delay. As such, there is a need to reduce this delay and achieve faster real time processing of data. This paper proposes a novel architecture for implementation of signed multiplication using the vedic algorithm. An 11×8 bit multiplier was designed using the proposed architecture and implemented using Xilinx ISE Design Suite 13.2 with Spartan 3E as the target FPGA. The maximum clock speed achieved was 203.938 MHz.