Design of low Power memory cell using D Flip Flop under adiabatic reduction

The dissipation of Power in conventional CMOS circuits can be minimized by adiabatic technique. In this paper, the energy consumption in conventional CMOS logic and implementation with adiabatic reduction technique for various types of D Flip Flops and their static and average powers are computed. Average power consumed can be reduced from 17.62% to 52.52% along with average power saving before and after layout was also calculated. From the simulations results, it could be concluded that the Power PC D Flip Flop exhibited best performance as compared to other D Flip Flops. The circuits have been simulated at transistor level using Cadence Virtuoso Tool at 180 nm CMOS process technology at VDD=1.8V and T=27°C.