Notice of Violation of IEEE Publication Principles: Elastic buffer for Virtual Channels in heterogenous switching Network on Chip

Notice of Violation of IEEE Publication Principles "Elastic Buffer for Virtual Channels in Heterogeneous Switching Network on Chip" by Gowthaman T.V. and Mugilan D. in the Proceedings of the IEEE 2016 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), September 2016, pp. 2045-2048 After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE's Publication Principles. This paper duplicated content from the paper cited below. The original content was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission. "ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip" by Ioannis Seitanidis, Anastasios Psarras, Kypros Chrysanthou, Chrysostomos Nicopoulos, and Giorgos Dimitrakopoulos in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, September 2015, pp.1-14.
The Network on Chip is the recent pattern, adopted in all types of systems on chip (SoCs) for reducing the complexity of system integration at the IP assembly level and from logical design to physical verification stage. On-chip network also enhances the system performance by partitioning the system cores and parallelizing the process. NOC provides the best solution to the wire delays and hence low latency period and high throughput has been achieved. The architecture of the router buffer is a critical design feature that affects both performance and implementation. Buffer architectures to support multiple Virtual Channels called Elastistore, which minimize the requirements of buffering without waiving the performance. A Virtual channel is the time multiplexed physical channel have different traffic flits, provided that separate buffer space for each flits. Elastistore having only single register per VC, round trip time appeared in NoC link is achieved by a large sized shared buffer. Elastistore integrated NoC gives efficient design at low cost along with similar performance. Area and delay of the router architecture were reduced considerably.