Verification of a RISC processor IP core using SystemVerilog

This paper describes a SystemVerilog Open Verification Methodology (OVM) for a 32 bit RISC processor IP core. For verification process a configurable and extensible test-bench is created which serves as the framework and it offers components necessary for the complete processor verification. To perform the verification, a behavioral model of the processor has to be created in the predictor block of the layered testbench. Open Verification Methodology has been adopted to make flexible programmable testbenches in the place of complex hardware targets.