High speed energy efficient carry skip adder operating at different voltage supply

The performance and efficiency of conventional carry skip adder structure is improved by employing increment and concatenation scheme. In the existing system the multiplier is used which consumes more power. Instead of using this structure that consists of AND-OR-INVERTER (AOI) and OR-AND-INVERTER (OAI) is used for skip logic. Further development in energy and speed can be achieved by the structures with both variable and fixed stage size. A hybrid variable latency structure of carry skip adder consist of a modified parallel structure with a prefix adder consist of a modified parallel structure with a prefix adder to reduce the power consumption and slack time. The parameters like power speed and delay of the proposed adder structure is compared with the other adders in CMOS technology. The result shows that the energy and delay is improved by 36% and 40% respectively.