Implementation of area and power efficient built in self Test Pattern Generator

As the technology is changing at grater pace there is a necessity to develop the devices that are efficient with respect to area and power. This paper presents a hybrid type BIST TPG which is efficient with respect to power and area. The proposed BIST TPG comprises of two types of BIST TPG's one is Modified Low Transition Random Test Pattern Generator (MLRTPG) and the other is Adder based 3-Weighted Random Test Pattern Generator (A3WRTPG). The MLRTPG aims at reducing power dissipation during BIST activity where as A3WRTPG aims at reducing the area overhead and improving the fault coverage of the BIST TPG. The MLRTPG achieves power dissipation by reducing the transitions that are associated with Circuit under Test (CUT) during BIST operation. The A3WRTPG aims at reducing the area overhead by employing Adders and D-flip flops to alter the weights of weighted deterministic BIST TPG to achieve improvement in detection probabilities of BIST TPG to detect Random Pattern Resistant Faults. The testing of proposed BIST TPG is carried under two phases. The first phase of testing is carried out by MLRTPG to detect easy-to-detect faults and the second phase of testing is carried out A3WRTPG to detect the faults that are dropped out by MLRTPG. The reduction of power and area of proposed BIST TPG also achieves significant improvement in parasitic capacitance which is the major dominating source of different circuit parameters.