A Configurable and Lightweight Timing Monitor for Fault Attack Detection

In this paper, we propose a cycle-accurate monitor that can efficiently detect timing violation based fault attacks. The proposed monitor detects clock or voltage manipulations by monitoring the external clock using an internal Ring Oscillator. The monitor is low cost in terms of area and power consumption and can be easily implemented using the standard cell based VLSI design flow. In addition to the architecture of the timing monitor, we present a detailed analysis on the design considerations that affect the cost and accuracy of the monitor. To validate the functionality of the monitor, we implemented it on Spartan-6 FPGA. We also synthesized our monitor onto IBM 90nm ASIC technology to examine the effects of process variation and aging. We show that the proposed method brings 0.23% area and 1.4% power overhead on a reference AES-128 hardware implementation.