Fracture-mechanics based delamination growth prediction in the very small periphery array (VSPA/sup TM/) package

Interfacial delamination due to dissimilar material systems is a primary concern in electronic package design. CTE mismatch between layers can generate high interfacial stresses under thermal loads during fabrication, assembly and/or field-use conditions which can compromise interface adhesive integrity. Delamination propagation along such interfaces can degrade or destroy package functionality. This study aims to predict interfacial delamination propagation potential in a novel surface mountable, high I/O very small peripheral array (VSPA/sup TM/) package. Delamination growth prediction is based on comparison of interfacial fracture parameters obtained from numerical simulations to critical values determined experimentally using controlled fracture toughness tests. 2D/3D VSPA/sub TM/ package numerical models were constructed with interfacial cracks embedded at critical locations. The energy release rate associated with interfacial fracture was determined using global energy balance and a crack closure technique. The fracture mode mixity was determined using a crack surface displacement method. A material parametric study was also completed using numerical models with pre-existing delaminations to identify material property trends that would lower the failure potential. For a baseline materials suite, the fracture parameters were compared with experimentally determined critical interfacial fracture toughness data to ascertain the possibility of delamination growth. Interface fracture toughness was characterized using a test method that requires simple test specimen, fixture and loading geometries, and a data reduction method.