Investigation of Output Voltage Ripple of Synchronous Buck DC-DC Converters

In standard practice, a DC-DC converter's output voltage ripple is minimized for accurate DC regulation. However, with the increasing demand for fast dynamic response performance, ripple-based regulators are being studied in greater depth to address system performance requirements. To utilize the benefits of these regulators, having a greater understanding of the output ripple mechanism becomes more and more important. In this paper, the influence of components and system operation on the synchronous buck converter's output voltage ripple are analyzed and compared. Practical design considerations are proposed for different cases, and SIMPLIS simulation and bench data are provided to validate the theory.