A novel device design to lower the on-resistance in GaN trench MOSFETs

GaN is one of the best suited materials for high-power devices due to its superior material properties such as high breakdown field, wide band gap and high saturation drift velocity. Consequently, GaN power devices have gained increased attention in recent years. Numerous vertical GaN power transistors have been demonstrated in the past few years [1-4]. One of the preferred GaN vertical device designs is the trench MOSFET. In the traditional trench MOSFET structure [2-4], the channel forms via p-GaN inversion at the dielectric/p-GaN interface resulting in a relatively high on-resistance due to the poor electron mobility in the channel. In this work, we present a novel device design to lower the on-resistance in a trench MOSFET. By inserting a MOCVD regrown GaN interlayer prior to the dielectric deposition (MOCVD Al₂O₃) on the trenched structure, lower on-resistance is achieved due to enhancement in the electron mobility of the channel. For an optimal GaN interlayer thickness of 10 nm, a low on-resistance (active area) of 0.97 mΩ.cm² alongside enhancement mode operation (V_th = 3 V) is demonstrated.