Implementation of a Fast Hybrid CORDIC Architecture

COordinate Rotation Digital Computer (CORDIC) algorithm was introduced for performing computing tasks such as the calculation of trigonometric, hyperbolic and logarithmic functions, real and complex multiplications and many more using simple add and shift operation. Recent years has witnessed an increasing trend in the FPGA implementation of CORDIC algorithm due to its simplicity in architecture. The conventional architecture has a drawback of latency bottleneck. To overcome this bottleneck, different architectures of CORDIC algorithm have been proposed like Hybrid CORDIC architecture, high radix architecture, angle recording method etc. This paper presents Verilog Hardware Description Language (HDL) implementation of CORDIC hybrid architecture and compares it with parallel architecture using Xilinx ISE Webpack and Synopsys Design Vision. Comparative analysis has indicated that hybrid architecture is fast as compared to parallel architecture but at the cost of power consumption and accuracy.