Impact of 3D Via Middle TSV Process on 20nm Wafer Level FEOL and BEOL Reliability

The impact of after level reliability of TSV has been studied with respect to FEOL (Front End of Line) and BEOL (Back End of Line) and aspects. A TSV keep out zone (KOZ) study has been done with varying gate length and width of transistor. Gate voltage (Vg) vs saturation current (Idsat) plots show that there is negligible impact on Idsat due to mechanical stress of the TSV for <; 3μm KOZ for both NFET and PFET devices fabricated with thin and thick gate-oxide dielectric. Voltage/Ramp Stress (VRS) and Constant Voltage Stress (CVS) tests were performed to analyze FEOL reliability for degradation phenomena such as Voltage Break Down (VBD), Hot Carrier Injection (HCI), and Bias Temperature stability (BTI). Test structures were designed to investigate TSV impact on the lower metal and via levels of the BEOL stack. BEOL reliability analysis for degradation phenomena such as Time Dependent Dielectric Breakdown (TDDB), Electromigration (EM), and Stress Migration (SM) were performed to investigate any potential impact to due to TSV mechanical stress or Cu pumping effects. BEOL Our investigations showed no significant impact to FEOL or BEOL test structures due to the TSV via middle approach.