Behavioral Circuit Models of Data Clocked and Reference Clock Driven Retimers for Signal Integrity Transient Simulation

Two different behavioral circuit models are proposed in this paper, one for the data clocked retimer and the other for the reference clock driven retimer. Instead of two or more piping simulations, the proposed retimer behavioral models can be used in any general purpose transient simulation tools by a single transient simulation. The proposed retimer behavioral circuit models are in a sub-circuit form and can be used directly and independently. The retimer behavioral circuit models include several new building block models such as a behavioral circuit model of signal rise-fall edge trigged latch, a behavioral circuit model of the reference clock driven latch, a behavioral circuit model of the CDR based on the jitter transfer function of the applied clock architecture, a behavioral circuit model of the lossy clock channel, and a behavioral circuit model of the clock frequency N-multiplier. The proposed retimer models also include some existing models such as a behavioral circuit models of a time-domain jitter to data stream modulator, a bidirectional single-ended-mode to mixed-mode transformer, and behavioral circuit models for CTLE, DEF, and pre-emphasis Tx. To include the low frequency periodic jitter, a time-frequency scaling method is proposed to use a much shorter circuit time for affordable signal integrity transient simulations. The transient circuit simulation for eye-diagram by using the proposed retimer behavioral circuit models can include the periodic, ISI induced, and crosstalk induced jitters in signal and/or clock channels. The proposed retimer behavioral circuit models are tested in transient circuit simulation on packaging systems including active twinaxes and on printed circuit board wires. No convergence problem appears during the test simulations. The simulation results look reasonable and have been verified by different methods.