Improving Copper Pillar Interconnection on Embedded Trace Substrates

In the push for thinner packages for application processors, baseband processors, and other devices, Embedded Trace Substrates (ETS) have found quick adoption in the microelectronics packaging industry. ETS offer several benefits over conventional cored substrates, such as dielectric layer thickness reduction, layer count reduction, and lower manufacturing costs. In parallel, copper pillar interconnects have become a standard for devices that fall into the Flip Chip/Chip Scale Package (fcCSP) envelope. Copper pillar technology provides long-term reliability, high bumping yields, and very fine pitch interconnects, all of which have become mandatory attributes for advanced devices. As a result, copper pillar technology with ETS is now a popular choice for low-cost, robust solutions to many of the most demanding device applications. While ETS have many benefits, they suffer risks which cored Protruded Trace Substrates do not, namely, a reduced trace surface area for first-level interconnection and an inherent pad recess below the substrate surface. Both of these characteristics increase the risk of non-wets occurring during chip attach in device assembly. In order to take full advantage of the benefits of copper pillar technology and ETS, reliability risks must be reduced to a minimum. The present paper seeks to do so by identifying the key geometric variables involved in the chip attach process of copper pillar bumps on ETS and developing a mathematical model to understand how each variable plays a role in the wetting outcome of the chip attach process. The intended goal of this paper is to provide a useful tool to predict and ultimately reduce the risk of non-wets.