Wet Etched Silicon Interposer for the 2.5D Stacking of CMOS and Optoelectronic Dies

In this paper, we demonstrate a way of packaging CMOS ICs and optoelectronics, which has been achieved by using a deeply wet etched silicon interposer. The silicon interposer concept is used for the assembly of electronics (drivers, TIAs), photonics (VCSELs, PDs) and mechanical optical interface (MOI) and can be fabricated on full wafers. Only four steps of lithography are needed to fabricate the silicon interposer and both sides of this interposer are utilized for electrical and optical connections. The impedance matched metal traces and gold bumps for electrical connection are lithographically transferred and electro-plated. The optical vias are also opened by wet etching. The process is performed on a diced 1 inch silicon wafer, 4 interposers are made with one process flow. The obtained silicon interposers are used for 12 × 10G transmitter and 4 × 25G transceiver. The process challenges for the 3D patterning of the silicon interposer and for the metal traces definition are discussed. Data integrity experiments are performed.