A 10-bit 10 MS/s SAR ADC with the reduced capacitance DAC

This paper presents a 10-bit 10 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 180 nm technology. We propose a new structure of the charge redistribution digital-to-analog converter (DAC) for the SAR ADC to reduce the area cost and power consumption and to promote the bandwidth. This structure does not only reduce the area of capacitors array and the capacitance of the DAC, but also guarantee the process variation of capacitors.