Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor

This column features retrospectives from the authors of six MICRO Test of Time award-winning papers: "MIPS: A Microprocessor Architecture" by Norman Jouppi and colleagues; "HPS, A New Microarchitecture: Rationale and Introduction" by Yale Patt, Wen-Mei Hwu, and Mike Shebanow; "Critical Issues Regarding HPS, A High Performance Microarchitecture" by Yale Patt and colleagues; "Hardware Support for Large Atomic Units in Dynamically Scheduled Machines" by Steve Melvin, Mike Shebanow, and Yale Patt; "Two-Level Adaptive Training Branch Prediction" by Tse-Yu Yeh and Yale Patt; and "Executing Compressed Programs on an Embedded RISC Architecture" by Andy Wolfe and Alex Chanin.