A 10 GHz phase noise filter with 10.6 dB phase noise suppression and −116 dBc/Hz sensitivity at 1 MHz offset

This paper presents a phase noise filter technique enabled by the delay-line and PD/CP based frequency discriminator with fully automatic calibration. It features wide bandwidth and insensitivity to amplitude noise. At low/high gain mode, it achieves 10.6/15 dB phase noise suppression with −116/−114.9 dBc/Hz sensitivity at 1 MHz offset, respectively. The suppression bandwidth is 100 kHz–10 MHz with input operating frequency range of 9.99–10.10 GHz. This proof-of-concept design is fabricated in a 65 nm CMOS process with the chip area of 1.68 mm × 1.5 mm. The circuit consumes 102 mW power.