An improved test power optimization method by insertion of linear functions

Scan-based design-for-testability (DFT) structure is widely used to facilitate the testing of integrated circuits (ICs). However, it always incurs much test power consumption. In this paper, we propose an improved test power optimization method by inserting extra logic in scan chain. It explores suitable places in scan chain based on an accurate criterion to insert different linear functions so as to minimize the transitions caused by shifting test data through scan chain. We apply our method on different benchmark circuits and the experimental result shows that the proposed method is more efficient to reduce test power than other optimization methods by inserting extra logic while incurring low area.